How to use function's variables inside function's scope in VHDL?

How to use function's variables inside function's scope in VHDL?

Actually I'm new in VHDL, I'm trying to assign a function's variable to a
variable declared in functions scope. But I'm getting an error when I'm
synthesizing. I'm using ISE Project Navigator. Here's my code.
function moverDerecha(datos : std_logic_vector(2 downto 0)) RETURN
std_logic_vector(2 downto 0) IS
variable TMP : datos;
--TMP := datos;
begin
TMP(0)<=TMP(2);
TMP(1)<=TMP(0);
TMP(2)<=TMP(1);
return TMP;
end moverDerecha;
I hope you could help me! It's part of my homework n.n.